This book includes a selection oftopics intended to make it useful to readers with a wide range of previous exposure to the field. Chapters l through 5 cover many of the basic concepts in computer organization including how performance is pro 6 and 7 cover pipelining and instruction-level parallelism. two technologies that are extremely important to the performance ofmodem processors. Chapters 8, 9, and I O cover memory system design. including memory hierarchies, caches, and virtual memory. Chapter II describes I/0 systems, while Chapter 12 provides an inuoduction to multiprocessor systems----computers that combine multiple processors to deliver improved performance.

One of the most interesting aspects of computer architecture is the rate at which the field changes. Innovation occurs on an almost-daily basis. offering opportunities for individuals　to contribute to the field. Homever, this rate of progress is one of the greatest challenges to teaching computer architecture and organization. Unlike many other fields, courses in computer architecture and organization must change on a term-by-term basis to incorporate new development in the field without overloadine students with material. Writing textbook for the field is similarly difficult as the author must find a balance between cutting-edge material and historical perspective.
　　This book includes a selection oftopics intended to make it useful to readers with a wide range of previous exposure to the field. Chapters l through 5 cover many of the basic concepts in computer organization including how performance is pro 6 and 7 cover pipelining and instruction-level parallelism. two technologies that are extremely important to the performance ofmodem processors. Chapters 8, 9, and I O cover memory system design. including memory hierarchies, caches, and virtual memory. Chapter II describes I/0 systems, while Chapter 12 provides an inuoduction to multiprocessor systems----computers that combine multiple processors to deliver improved performance.
　　It is my hope that readers will find this book useful in their study of the field. I have tried to make my explanations of each topic as clear as possible and to avoid getting bogged down in detail. Compressing the field of computer architecture and organization into a book this size was a challenge, and I look forward to any comments that readers may have about the selection of material, the exercises, or anyaling else related to this work. '
　　In conclusion, I would like to thank an those who have made this effort possible:my parents, my friends, my coneagues at the University of Illinois, and all of the teachers who contributed to my own education. In addition, I would like to thank the staff at McGraw-HiII for encouraging this work and for their tolernce of schedule delays.

CHAPTER I Introd　 uction
l .l Purpose of This Book
l .2 Background Assumed
l .3 Material Covered
l .4 Chapter Objectives
l .5 Technological Trends
l .6 Measuring Performance
l .7 Speedup
l .8 Amdahl's Law
l.9 S
- Solved Problems
CHAPTER 2 Data Representations and Computer Arithmetic
2. l Objectives
2.2 From Electrons to Bits
2.3 Binary Representation of Positive Integers
2.4 Arithmetic Operations on Positive Integers
2.5 Negative Integers
2.6 Floating-Point Numbers
2.7 S
Solved Problems
CHAPTER 3 Computer Organization
3. I Objectives
3 .2 Introduction
3 . 3 Programs
3 .4 Operating Systems
3 .5 Computer Oganization
3.6 Summary
Solved Problems
CHAPTER 4 Programming Models
4. l Objectives
4.2 Introduction
4.3 Types of Instructions
4.4 Stack-Based Architectures
4.5 General-Purpose Register Architectures
4.6 Comparing Stack-Based and General-Purpose Register
Architectures
4.7 Using Stacks to Implement Procedure Calls
4. 8 Summary '
Solved Problems
CHAPTER 5 Processor Design
5 .l Objectives
5 .2 Introduction
5 .3 Instruction Set Architecture
5 .4 Processor Microarchitecture
5.5 S
Solved Problems
CHAPTER 6 Pipelining
6. l Objectives
6 .2 Introduction
6. 3 Pipelining
6.4 Instruction Hazards and Their Impact on Throughput
6.5 Predicting Execution Time in Pipelined Processors
6.6 Result Forwarding (Bypassing)
6.7 S
Solved Problems
CHAPTER 7 Instruction-Level Parallelism
7. l Objectives
7 .2 Introduction .
7.3 What is Instruction-Level Parallelism
7.4 Limitations of instruction-Level Parallelism
7.5 Superscalar Processors
7.6 In-Order versus Out-of-Order Execution
7.7 Register Renaming '
7.8 VLIW Processors
7.9 Compilation Techniques for Instruction-Level Palallelism
7.IO S
Solved Problems
CHAPTER 8 Memory Systems
8. l Objectives
8 .2 Introduction
8.3 Latency, Throughput and Bandwidth
8.4 Memory Hierarchies
8.5 Memory Technologies
8.6 S
Solved Problems
CHAPTER 9 Caches
9. l Objectives
9.2 Introduction
9.3 Data Caches, Instruction Caches, and Unified Caches
9.4 Describing Caches
9.5 Capacity
9.6 Line Length
9 .7 Associativity
9.8 Replacement Policy
9.9 Write-Back versus Write-Through Caches
9. IO Cache Implementations
9.Il Tag Arrays
9.12 Hit/Miss Logic
9.13 Data Arrays
9. 14 Categorizing Cache Misses
9.15 Multilevel Caches
9.16 S
Solved Problems
CHAPTER IO Virtual Nemory
l0.l Objectives '
10.2 Introduction
10.3 Address Translation
10.4 Demand Paging versus Swapping
10.5 Page Tables
10.6 Translation Lookaside Buffers
10.7 Proteaion
10.8 Caches and Virtual Memory
10.9 Summary
Solved Problems
CHAPTER Il I/O
l l.l Objectives
l l.2 Introduction
1l.3 I/0 Buses
l l.4 Interrupts
l I.5 Memory-Mapped I/O
l l .6 Direct Memory Aceess
I l.7 I/O Devices
l l.8 Disk Systems
11.9 S
Solved Problems
CHAPTER I 2 Multiprocessors
12.1 Objectives
12.2 Introduction
12.3 Speedup and Performance
1 2.4 Multiprocessor Systems
12.5 Message-Passing Systems
l 2.6 Shared-Memory Systems
12.7 Comparing Message-Passing and Shared Memory
12.8 Summary
Solved Problems
INDEX